1. Field of the Invention
The present invention generally relates to a semiconductor device, and more particularly, to a semiconductor device which can prevent a latch-up phenomenon.
2. Description of Related Art
Semiconductor design must be improved along with increasing integration and increasing complicated requirements thereof. For example, the design of high voltage devices must enable the devices to operate under a high voltage without effecting operation of other devices. Restriction and problem of a high voltage device are described as follows with reference to FIG. 1.
FIG. 1 is a cross-sectional view showing a conventional high voltage device. This high voltage device is a complementary metal-oxide-semiconductor field effect transistor (CMOSFET) that is composed of two lateral double-diffused metal-oxide-semiconductor field effect transistors (LDMOSFET).
With reference to FIG. 1, the high voltage device comprises a P-type substrate 100, gates 102 and 104, gate dielectric layers 105 and 108, a P-well 112p, a P-tub 114p, doped regions 116p, 118p and 120p, N-tubs 122n and 124n, doped regions 126n, 128n and 130n, an isolation structure 134, a dielectric layer 136, interconnects 138, and a dielectric layer 140. The P-type substrate 100 may be divided as a region of HVNMOSFET and a region of HVPMOSFET containing an high voltage N-type metal-oxide-semiconductor field effect transistor (hereinafter referred to as N-type MOSFET) and a high voltage P-type metal-oxide-semiconductor field effect transistor (hereinafter referred to as high voltage P-type MOSFET), respectively. The doped regions 126n, 128n and the gate 102 form respective source, drain and gate of the high voltage N-type MOSFET, and the doped regions 120p, 118p and the gate 104 form respective source, drain and gate of the high voltage P-type MOSFET. The doped regions 116p, 118p and 120p have a P+-type conductivity, and the doped regions 126n, 128n and 130n have an N+-type conductivity.
The high voltage device as shown in FIG. 1 has the following shortcomings:
1. The high voltage device may leads to a latch-up phenomenon. Specifically, the doped regions 120p, N-tub 124n and P-type substrate 100 constitute the emitter, base and collector of a parasitic bipolar transistor, the doped regions 126n, P-type substrate 100 and N-tub 124n constitute the emitter, base and collector of another parasitic bipolar transistor. Once a product of current gains of the two parasitic bipolar transistors is greater than “1,” the high voltage device can not operate normally.
2. The high voltage P-type MOSFET and high voltage N-type MOSFET are formed on the P-type substrate 100. An input voltage applied to the doped region 120p will be directly applied to the P-type substrate 100. Therefore, the input voltage is subject to a great restriction, resulting in a narrowed operation voltage range of the high voltage device.
3. The P-type substrate 100 usually includes other semiconductor devices formed thereon. However, the high voltage device has no isolation structures formed at two sides thereof. As a result, the high voltage device and these other semiconductor devices may interfere with each other.
Therefore, the operation of any semiconductor device can possibly effect the operation of any others. It is thus desired to provide an improved solution addressing the above-mentioned shortcomings and problems.